The inventive concept generally relates to semiconductor devices, and more particularly, to semiconductor devices which may include metal oxide semiconductor (MOS) capacitors.
As multi-functional and compact devices are frequently used in electronic apparatuses, highly integrated system-large scale integrated circuits (LSIs) have been developed. In a process of manufacturing a logic integrated circuit (IC)-based system LSI, devices, such as a memory device, a high voltage transistor or a logic IC, are formed on the same substrate, and thus, a highly integrated system LSI additionally includes a storage function and a power management function. Along with the miniaturization of system LSIs, sizes of logic ICs included therein have also been reduced according to a size scaling rule for IC devices.
In addition, devices having a relatively high well doping concentration are needed according to the scaling of IC devices, and also, when forming such devices, a MOS capacitor that is used as a varactor may also be formed to implement a system on chip (SOC). However, when a MOS capacitor is formed on a substrate having a relatively high well doping concentration, a minimum capacitance (Cmin) may increase in a depletion operational state when a depletion layer is formed at an interface between an insulating layer and a semiconductor in the MOS capacitor. As a result, a range between a maximum capacitance (Cmax) and the minimum capacitance (Cmin), which determines a tuning range of the MOS capacitor, becomes narrow, and thus, the tunability of a the MOS capacitor may deteriorate.